First China RISC-V Forum held at Tsinghua SIGS, A.M. Turing Award RIOS Laboratory unveiled

The first China RISC-V Forum, with the theme of “Ecosystem Wants to be Free”, was held at Tsinghua Shenzhen International Graduate School (Tsinghua SIGS) on November 12 to 13. During the forum, the RISC-V International Open Source Laboratory was officially unveiled.

Global scholars and industry experts gathered at the two-day forum which aims to identify challenges in building an open RISC-V ecosystem, and shed light on industrial and academic efforts in the RISC-V landscape including but not limited to RISC-V processor design, design tools, system software, IP cores and SoCs.

Dr. David Patterson, 2017 A.M. Turing Award winner and Pardee Professor of Computer Science Emeritus at UC Berkeley delivered the keynote speech, while Co-director of Tsinghua-Berkeley Shenzhen Institute (TBSI) and Executive Dean of Tsinghua SIGS Gao Hong also addressed at the event. The Forum was chaired by Tan Zhangxi, Deputy Director of RIOS Laboratory and Adjunct Professor of TBSI.


Site of the Forum 


Co-director of Tsinghua-Berkeley Shenzhen Institute (TBSI) and Executive Dean of Tsinghua SIGS Gao Hong delivering a speech 


Dr. David Patterson delivering the keynote speech 

Executive Dean Gao Hong expressed in her opening speech that the Fifth Generation Reduced Instruction Set (RISC-V) is a key open source technology that will profoundly impact the next-generation information technology industry, and enrich the development of Tsinghua SIGS in areas of data science and information technology. She expressed hopes that the RISC- V Forum can serve as a platform for exchange to promote the construction of an open source software and hardware ecosystem.

The forum involved a series of keynote speeches, thematic talks and panel discussions. In his keynote speech, Dr. Patterson introduced the five year mission of RIOS Laboratory and gave an general overview of the origins and current state of RISC-V. Deriving its name from the Spanish word for “rivers”, Dr. Patterson conveyed high hopes for RIOS Laboratory to collect resources from many avenues to create a strong force that transforms the RISC-V landscape. Guest speakers addressed current topics in the RISC-V landscape including Security, Deep Learning, Support and Verification, Architecture as well as System Software and Compilers. Panel discussions on the topics of “Venture Capital and Investment for RISC-V in China” and “RISC-V Applications and Ecosystem”, allowed enterprise representatives and guests to explore ways to construct an open and free RISC-V ecosystem and its application in China.

Invited guests include Calista Redmond, CEO of RISC-V Foundation; Ted Speers, Director of RISC-V Foundation and Vice-President of Micro-Chip; Alex Wang, President of Powerchip Technology and Chairman of RISC-V Taiwan Alliance; Shijiang Wang, Director of China Center for Information Industry Development IC Industry Research Institute; Pascal Jiang, Partner at Dentons; and   Zvonimir Bandic, Senior Director of Western Digital Corporation.



Photo of guests at the First China RISC-V Forum 

In the afternoon of November 12, the unveiling ceremony of the RISC-V International Open Source Laboratory (RIOS) was held. Director of RIOS Dr. Patterson and Deputy Director Tan Zhangxi joined Shenzhen’s Vice Mayor Wang Lixin, Director of Talent Supporting Office Zhang Lin, Deputy Director of Science, Technology and Innovation Commission of Shenzhen Municipality Zhong Hai and Executive Dean of Tsinghua SIGS Gao Hong in jointly unveiling the RIOS Laboratory. The ceremony was hosted by Victor Chan, Vice-President of TBSI. 


Unveiling ceremony of the RISC-V International Open Source Laboratory (RIOS) 

(From left: Deputy Director of RIOS Tan Zhangxi, Executive Dean of Tsinghua SIGS Gao Hong, Director of RIOS David Patterson, Shenzhen Vice Mayor Wang Lixin, Director of Talent Supporting Office Zhang Lin, Deputy Director of Science, Technology and Innovation Commission of Shenzhen Municipality Zhong Hai) 

Under the leadership of Dr. Patterson and operational support from TBSI, RIOS Lab will conduct cutting-edge research in RISC-V hardware and software technology. Patterson first proposed the Reduced Instruction Set (RISC) system, an open and free instruction set architecture enabling a new era of processor innovation through open standard collaboration. Released in 2011, the latest Fifth Generation Reduced Instruction Set (RISC-V) has gained worldwide attention.

The RIOS Laboratory will accelerate the industrialization of global RISC-V technology and its wide industrial application in the world. It will respond to development trends in the global CPU industry, needs of Guangdong-Hong Kong-Macao Greater Bay Area enterprises and elevate the RISC-V ecosystem to state-of-the-art.

Currently accepting graduate applications for 2020, RIOS Laboratory will provide graduate-level education under the Data Science and Information Technology discipline at TBSI. The program plans to enroll 10 students for its first year, and aim to increase student enrollment to 100 within the next five years. Students will take courses related to RISC-V and computer systems, conduct research training under the guidance of the RIOS Laboratory team. With future plans for doctoral programs and postdoctoral work, RIOS Laboratory will become a platform where students, scholars and industry experts can share and explore cutting-edge development trends of RISC-V.

The establishment of RIOS Laboratory in Shenzhen also has far-reaching significance. It will attract and nurture high-end talents in processor and open source hardware design, build a RISC-V global innovation network rooted in Shenzhen, contribute to the construction of Shenzhen’s international technology ecosystem and intelligent hardware industry, and enhance the influence of the Greater Bay Area in the global RISC-V ecosystem.

The creation of diverse communication platforms where experts can share and collaborate on cutting-edge technology is key to open source development. The First China RISC-V Forum marks the gradual formation of a new RISC-V ecosystem and a new golden age for computer architecture.

The China RISC-V Forum is organized by RIOS Laboratory, RISC-V Foundation China Committee, China RISC-V Alliance (CRVA) and co-organized by TBSI.  


Article by Karen Lee